A low temperature poly-silicon (LTPS) thin film transistor liquid crystal display, compared with the traditional amorphous silicon thin film transistor liquid crystal displays, has high electron mobility, which can not only effectively reduce the area of a thin film transistor device to improve aperture ratio, but also reduce power consumption while enhancing brightness of the display. In addition, the relatively high electron mobility allows part of drive circuits to be integrated onto a glass substrate to reduce cost of the drive circuits, and can further greatly enhance the reliability of a liquid crystal display panel, thus greatly reducing the fabricating cost of the panel. Hence, the low temperature poly-silicon thin film transistor liquid crystal display has gradually become a hotspot of research.
FIG. 1 shows a schematic structure diagram of a low temperature poly-silicon thin film transistor in the prior art. As shown in FIG. 1, a source 12 and a drain 13 both come into contact with an active layer 11 through via holes, and in this way, the distance between the drain and a pixel electrode on an array substrate may be decreased, so as to facilitate connection between the pixel electrode and the drain. However, as shown in FIG. 2, in the prior art, an over etching phenomenon is likely to occur during etching the via hole, resulting in poor contact between the source 12, the drain 13 and the active layer 11 after the source 12 and the drain 13 are formed, thus reducing the reliability and yield of the thin film transistor.